Improvements in both speed and functionality of personal computers and multimedia systems have generally resulted in accompanying improvements in memory devices to support the operation of these products. Various methods have been developed to increase the operational speed of integrated circuit memory devices. One approach to increasing the operational speed of integrated circuit memory devices may involve increasing the transmission speed of signals on data paths, such as the write data path and the read data path, which are used to write data to a memory cell and read data stored in a memory cell, respectively. It may also be desirable to decode a memory cell address at high speed to allow high-speed selection of a memory cell. In this regard, it may be particularly advantageous to decode row addresses at high speed to allow high-speed selection of a row or a word line.
With reference to FIG. 1, a conventional integrated circuit memory device includes a row predecoder 11 and an internal master signal generator 13. The internal master signal generator 13 is coupled to both the row predecoder 11 and an enable signal generator 15. The integrated circuit memory device further includes a row main decoder 17, which is coupled to a memory cell array 19. The row predecoder 11 and the enable signal generator 15 are both coupled to the row main decoder 17. Operations of the integrated circuit memory device of FIG. 1 will be described hereafter with reference to the signal timing diagram of FIG. 2.
A row address RAi and a row address strobe signal RAS (ie., external master signal) are provided as inputs to the row predecoder 11 and the internal master signal generator 13, respectively. As shown in FIG. 2, the row address RAi is provided for a predetermined length of time, tAS (ie., row address setup time) before the row address strobe signal RAS is activated (ie., driven to a logic 0 level). The internal master signal generator 13, in response to the activation of the row address strobe signal RAS, activates an internal master signal PR by driving the internal master signal PR to a logic 1 level. In response to the activation of the internal master signal PR, the row predecoder 11 predecodes the row address RAi and generates a predecoded row address DRAij.
After the internal master signal PR has been activated, the enable signal generator 15 allows a predetermined time interval tF to elapse before activating an enable signal PNBLS by driving the enable signal PNBLS to a logic 1 level. This delay provides the row predecoder 11 with time to generate the predecoded row address DRAij. The row main decoder 17 decodes the predecoded row address DRAij and activates a word line enable signal NWEi by driving the word line enable signal NWEi to a logic 1 level in response to the activation of the enable signal PNBLS. When the word line enable signal NWEi is activated, a corresponding word line in the memory cell array 19 is activated. Accordingly, a corresponding memory cell is selected from the memory cell array 19.
As illustrated in the foregoing discussion, decoding a row address in a conventional integrated circuit memory device typically involves at least two time delays: First, the row predecoder 11 waits for the internal master signal generator 13 to activate the internal master signal PR before predecoding the row address RAi. Second, the enable signal generator 15 delays a predetermined time tF before activating the enable signal PNBLS to provide the row predecoder 11 with time to generate the predecoded row address DRAij. As a result , conventional integrated circuit memory devices may take a relatively long time from the point in time at which the row address RAS is activated to the point in time at which the word line enable signal NWEi is activated.
Consequently, there exists a need for improved (e.g., higher speed) address decoding in integrated circuit memory devices.